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Semiconductor & VLSI ⚡ Device Physics · Digital IC · Wafer Fab · Physical Design ✔ 3 Levels Available

Semiconductor & VLSI
Full Programme

A comprehensive hands-on curriculum spanning the complete semiconductor lifecycle. Master solid-state electronic band theory, nanoscale FinFETs, CMOS digital standard cell design, analog and mixed-signal converters, wafer fabrication cleanroom operations, RTL verification (SystemVerilog/UVM), and physical design sign-off aligned with IEEE VLSI and global semiconductor industry standards.

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Format
Theory + Lab/Assignments
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Certificate
Arich Certified
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Course Code
SEMI-VLSI
Click a Level to View its Syllabus
L1
SEMI-FND · Associate
6 Modules · Physics, CMOS & Wafer Fab
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L2
SEMI-PRO · Professional
4 Modules · RTL, UVM & Synthesis
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L3
SEMI-SPEC · Specialist
4 Modules · Physical Design & Tape-Out
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📄 Semiconductor Lifecycle — Associate Level (SEMI-FND)
L1
SEMI-FND
Semiconductor Physics, IC Design & Wafer Fabrication Foundations
01
Semiconductor Physics & Device Fundamentals
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1.1 Electronic Band Theory & Nanoscale Physics
Band Theory of Solids: Conduction & Valence Bands, Direct vs Indirect Bandgaps
Carrier Statistics, Intrinsic vs Extrinsic Semiconductors & Fermi-Dirac Distribution
P-N Junctions, Depletion Region Dynamics, Breakdown Mechanisms & I-V Curves
Metal-Semiconductor Contacts (Schottky Barriers & Ohmic Contacts)
MOSFET Operating Physics (Subthreshold, Linear, Saturation) & Short-Channel Effects
FinFET & Gate-All-Around (GAAFET/Nanosheet) Transistor Architectures
Hands-on Lab: TCAD Simulation (Synopsys TCAD / Silvaco) of P-N junction I-V characteristics and 14nm FinFET threshold voltage drift
02
Fundamentals of Digital IC Design
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2.1 CMOS Logic & Standard Cell Design Principles
CMOS Inverter Static & Dynamic Characteristics, Switching Threshold (Vth) & Noise Margins
Combinational Logic Design: Static CMOS, Transmission Gates & Pass-Transistor Logic
Sequential Logic Circuits: Latches, Flip-Flops & Master-Slave Architectures
Clocking Strategies, Setup Time, Hold Time & Propagation Delay Analysis
Dynamic Power, Leakage Power Reduction & Sizing Optimization
Hands-on Lab: SPICE Simulation (HSpice / Cadence Virtuoso) of 7nm CMOS inverter delay, noise margins, and power consumption
03
Analog & Mixed-Signal Electronics
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3.1 Op-Amps & Data Converters Architecture
Single-Stage (CS, CG, CD) & Differential Amplifiers, Active Loads & Current Mirrors
Operational Amplifiers (Op-Amps): Two-Stage OTA, Frequency Response, Gain-Bandwidth (GBW) & Miller Compensation
Bandgap Voltage References (BGR) & Biasing Circuits
Analog-to-Digital Converters (ADCs): SAR, Sigma-Delta & Flash Converters
Digital-to-Analog Converters (DACs): Binary-Weighted, R-2R Ladder & Current-Steering
Hands-on Lab: Design & SPICE verification of 2-stage OTA with frequency compensation and 10-bit SAR ADC
04
Material Science & Wafer Fabrication Overview
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4.1 Wafer Substrates & Cleanroom Operations
Silicon Ingot Crystal Growth (Czochralski Method), Slicing, Polishing & Epitaxy
Cleanroom Protocols: ISO Classifications, Airborne Particulate Control & Ultrapure Water
Photolithography: Photoresists, Reticles, DUV 193nm Immersion & EUV 13.5nm Systems
Etching Processes: Wet Chemical Etch vs Dry Plasma Reactive Ion Etching (RIE/ICP)
Thin Film Deposition: Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD) & PVD Sputtering
Doping & Annealing: Ion Implantation, Junction Depth & Rapid Thermal Processing (RTP)
Hands-on Lab: Process Simulation of CMOS Front-End-of-Line (FEOL) Lithography & Etch Sequence in Silvaco Athena
05
RTL Design & Simulation with Verilog / SystemVerilog
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5.1 Front-End Hardware Description & Verification
Verilog / SystemVerilog Language Constructs & Synthesis Guidelines
Synchronous Finite State Machines (FSMs - Mealy vs Moore) & Datapath Design
Pipelining Architectures, Hazard Mitigation & Throughput Optimization
Clock Domain Crossing (CDC) Fundamentals: Synchronizers, Handshaking & Async FIFOs
Self-Checking Simulation Testbenches & Waveform Debugging with ModelSim / Questa
Hands-on Lab: Design, Simulation & Verification of an AXI4-Lite Memory Controller Core in SystemVerilog
06
Physical Design Fundamentals & Silicon Testing
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6.1 Back-End Physical Implementation & Design for Testability
ASIC RTL-to-GDSII Design Flow: Logic Synthesis, Floorplanning, Power Grid Design
Placement, Clock Tree Synthesis (CTS) & Global/Detail Routing
Physical Verification: Design Rule Checking (DRC) & Layout Versus Schematic (LVS)
Design for Testability (DFT): Scan Chain Insertion, Automatic Test Pattern Generation (ATPG) & BIST
Silicon Packaging: Wire Bonding, Flip-Chip BGA, Wafer-Level Packaging & ATE Post-Silicon Validation
Capstone Project: Complete RTL-to-GDSII Implementation of a 32-bit RISC-V Processor Core with DRC/LVS and Timing Sign-Off
📄 Semiconductor Lifecycle — Professional Level (SEMI-PRO)
L2
SEMI-PRO
Front-End RTL, UVM Verification & Logic Synthesis
01
Advanced SystemVerilog for Verification & UVM Framework
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SystemVerilog OOP: Polymorphism, Virtual Interfaces, Mailboxes & Semaphores
Constrained Random Verification (CRV) & Functional Coverage Models (Covergroups, Coverpoints)
Universal Verification Methodology (UVM) Architecture: UVM Drivers, Monitors, Scoreboards & Sequencers
TLM (Transaction-Level Modeling) 2.0 Communication & Virtual Sequences
Hands-on Lab: Build a Complete UVM Verification Environment with Scoreboard for a Multi-Channel DMA Controller
02
Logic Synthesis & Static Timing Analysis (STA)
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Logic Synthesis with Synopsys Design Compiler: Technology Mapping & Optimization
Standard Cell Library Characterization (.lib Liberty format) & Liberty Timing Models (NLDM / CCS)
Timing Constraints (SDC): Clocks, Generated Clocks, Input/Output Delays & Multi-Cycle Paths
Multi-Corner Multi-Mode (MCMM) Static Timing Analysis with Synopsys PrimeTime
Hands-on Lab: Constrain, Synthesize, and Perform Sign-Off STA on an AMBA AXI Interconnect Core
03
Low-Power Design Methodologies (UPF / CPF)
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Power Management Architectures: Power Gating, Multi-Threshold CMOS (MTCMOS) & Dynamic Voltage Frequency Scaling (DVFS)
Multi-Voltage Domains, Isolation Cells, Level Shifters & State Retention Power Gating (SRPG)
Unified Power Format (UPF / IEEE 1801) Specification, Power States & Supply Networks
Low-Power Verification & Simulation with Power-Aware Testbenches
Hands-on Lab: Implement UPF Power Intent for an IoT SoC with 3 Independent Power Domains and Verify Retention Sequences
04
Advanced Interconnects & High-Speed Protocols
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ARM AMBA Interconnects: AXI5, AHB5, APB & Cache Coherent Interconnects (ACE/CHI)
High-Speed Peripheral Interfaces: PCIe Gen5/6 Architecture & CXL (Compute Express Link)
Memory Subsystem Controllers: LPDDR5/DDR5 Architecture & DFI Interface
SerDes PHY Fundamentals: Equalization (CTLE, DFE), Clock Data Recovery (CDR) & Jitter
Hands-on Lab: Design and Verify a Pipelined AXI-to-APB Bridge with Asynchronous Clock Domain Crossing
📄 Semiconductor Lifecycle — Specialist Level (SEMI-SPEC)
L3
SEMI-SPEC
Advanced Physical Design, Chiplets, FinFET & Tape-Out Sign-Off
01
Advanced Physical Design & Sub-5nm Nanoscale Nodes
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Sub-5nm FinFET / GAAFET Design Rule Challenges, Self-Aligned Double/Quad Patterning (SADP/SAQP)
Hierarchical Floorplanning, Macro Placement & Power Grid IR Drop Mitigation
Clock Tree Synthesis (CTS): Mesh, H-Tree & Multi-Source CTS for Low-Skew Gigahertz Clocks
Dynamic IR Drop & Electromigration (EM) Sign-Off with Ansys RedHawk
Hands-on Lab: Full Place & Route (P&R) Flow for a 3GHz AI Accelerator Block on a 5nm PDK using Cadence Innovus / Synopsys ICC2
02
Advanced Packaging, Chiplets & Heterogeneous Integration
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2.5D Silicon Interposers (TSMC CoWoS, Intel EMIB) & Through-Silicon Vias (TSVs)
3D IC Stacking & Hybrid Bonding (Direct Copper-to-Copper)
UCIe (Universal Chiplet Interconnect Express) & BoW (Bunch of Wires) Open Standards
High-Bandwidth Memory (HBM3/HBM3e) PHY & Controller Integration
Thermal, Warpage & Signal Integrity Analysis for Multi-Die Systems
Hands-on Lab: Package-Level Co-Design & Signal Integrity Simulation for a Dual-Chiplet Processor with HBM3 Interposer
03
Advanced Analog / RF IC & Silicon Photonics
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RF CMOS Design: Low-Noise Amplifiers (LNAs), Mixers, Power Amplifiers & Voltage-Controlled Oscillators (VCOs)
All-Digital & Charge-Pump Phase-Locked Loops (PLLs) for Low-Jitter Clock Generation
Silicon Photonics (SiPh): Optical Waveguides, Mach-Zehnder Modulators & Photodetectors
Co-Packaged Optics (CPO) Architecture for Next-Generation Data Center Switches
Hands-on Lab: Design and Cadence Spectre-RF Simulation of a 10GHz Low-Phase-Noise LC-VCO and Phase-Locked Loop
04
Foundry Tape-Out, DFM Sign-Off & Yield Engineering
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Foundry PDK Integration (TSMC, GlobalFoundries, Intel 18A) & DRC/LVS/ERC Sign-Off with Mentor Calibre
Design for Manufacturability (DFM): Critical Area Analysis (CAA), CMP Metal Fill & Litho Hotspot Fixing
Optical Proximity Correction (OPC) & Reticle Mask Data Preparation (MDP)
Final GDSII / OASIS Delivery, Packaging Cleanroom Assembly & ATE Wafer Sort Testing
Capstone Project: Complete Tape-Out Sign-Off & GDSII Delivery for a Multi-Core Heterogeneous SoC with Full Calibre DRC/LVS Clearance